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Reiner Hartenstein

Publications

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The most cited publications by Reiner Hartenstein

A total of 3324 citations according to Google Scholar, October 1, 2013

Over 100 citations:

R Hartenstein: A decade of reconfigurable computing: a visionary retrospective;  Proc. International Conference on Design Automation and Testing in Europe 2001 (DATE 2001), Exhibit and Congress Center, Munich, Germany, March 2001  -  cited by  710  

W. Mangione-Smith, B. Hutchings, D. Andrews, A. DeHon, C. Ebeling, R. Hartenstein, O. Mencer, J. Morris, K. Palem, V. Prasanna, H. Spaanenburg: Seeking solutions in configurable computing; IEEE Computer, Vol. 30, No. 12, December 1997   -  cited by 220 

R Hartenstein: Coarse grain reconfigurable architecture (embedded tutorial); Proc. Asian and South Pacific Design Automation Conference 2001 (ASP-DAC'01), Yokohama, Japan, Jan 30 - Feb. 2, 2001  -  cited by  202 

R. Hartenstein, R Kress: A datapath synthesis system for the reconfigurable datapath architecture;
Proc Asia and South Pacific Design Automation Conference, ASP-DAC'95, Nippon Convention Center, Makuhari, Chiba, Japan, Aug./Sept. 1995  -  cited by  143 

Over 30 citations:

J Becker, R Hartenstein, M Herz, U Nageldinger: Parallelization in co-compilation for configurable accelerators-a host/accelerator partitioning compilation method; Proc.  Asia and South Pacific Design Automation Conf., ASP-DAC’98,  Yokohama, Japan, Feb 10-13, 1998  cited by 95     <2nd copy>

J Becker, R Hartenstein: Configware and morphware going mainstream; Journal of Systems Architecture 49 (4), 127-142   -  cited by  79 

R Hartenstein, M Herz, T Hoffmann, U Nageldinger: KressArray Xplorer: A new CAD environment to optimize reconfigurable datapath array architectures; 5th Asia and South Pacific Design Automation Conference 2000, ASP-DAC 2000, Yokohama, Japan, January 25-28, 2000  -  cited by 78 

R. Hartenstein, R Kress, H Reinig: A new FPGA architecture for word-oriented datapaths; Field-Programmable Logic Architectures, Synthesis and Applications, 4th Int. Workshop On Field Programmable Logic And Applications, FPL'94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994          -  cited by 75  

R Hartenstein: The microprocessor is no longer general purpose: why future reconfigurable platforms will win;  Proc. 2nd IEEE Symp on Innovative Systems in Silicon (ISIS), 1997.    cited by 73

R. Hartenstein, J Becker, M Herz, U Nageldinger: A General Approach in System Design Integrating Reconfigurable Accelerators; Proc. 8th EEE Symp. on Innovative Systems in Silicon, Austin, Texas, USA 1996  -  cited by 48  

R. Hartenstein: Fundamentals of Structured Hardware Design: a Design Language Approach at Register Transfer Level;  North-Holland Publishing Co., 1977  cited by  48 

R. Hartenstein, J Becker, R Kress: Custom computing machines vs. hardware/software co-design: From a globalized point of view;  6th Int'l Worksh on Field Programmable Logic and Applications; Darmstadt, Germany, Sep 23-25, 1996          -  cited by  46     <source>

R Hartenstein: Trends in reconfigurable logic and reconfigurable computing*; 9th IEEE International Conference on Electronics, Circuits and Systems: ICECS 2002, Sep 15-18, 2002, Dubrovnik, Croatia  <source?>  --  cited by 45

R. Hartenstein, M Herz, T Hoffmann, U Nageldinger: Using the KressArray for reconfigurable computing; Proceedings of SPIE Vol. 3526, Conference on Configurable Computing: Technology and Applications, Boston, USA, November 2-3, 1998  -  cited by  45 

R. Hartenstein, AG Hirschbiel, M Riedmuller, K Schmidt, M Weber: A novel ASIC design approach based on a new machine paradigm;  IEEE J. on Solid-State Circuits 26 (7),1991  -  cited by    45

M Herz, R Hartenstein, M Miranda, E Brockmeyer, F Catthoor: Memory addressing organization for stream-based reconfigurable computing; . Proc 9th International Conference on Electronics, Circuits and Systems (ICECS), September 15 - 18,2002. Dubrovnik, Croatia      -  cited by  42 

R. Hartenstein, A. G. Hirschbiel, K Schmidt, M Weber: A novel paradigm of parallel computation and its use to implement simple high-performance hardware; Future Generation Computer Systems 7 (2), 1991/1992  (reprinted)    -  cited by  41 

R Hartenstein: Reconfigurable computing: A new business model-and its impact on SoC design;
EUROMICRO Symp.on Digital Systems Design, Warzaw, Poland, Sep 4-6, 2001  -  cited by 36  

R. Hartenstein, J Becker, R Kress, H Reinig, K Schmidt: Reconfigurable machine for applications in image and video compression; European Symposium on Advanced Networks and Services: Conference on Compression Technologies and Standards for Image and Video Compression, Amsterdam, the Netherlands, March 1995 - Advanced Networks and Services, 9-20   -  cited by 36  

R. Hartenstein, AG Hirschbiel, M Weber: A novel paradigm of parallel computation and its use to implement simple high performance hardware; CONPAR 90—VAPP IV: Joint International Conference on Vector and Parallel Processing, Zurich, Switzerland, Sep 10-13, 1990 -  cited by 36 


Over 10 citations:

RP Jacobi, M Ayala-Rincón, LGA Carvalho, CH Llanos, R Hartenstein: Reconfigurable systems for sequence alignment and for general dynamic programming; Genetics and Molecular Research 4 (3), 2005, 543-552 - cited by 30 -  cited by 31 

R Hartenstein, AG Hirschbiel, M Weber: MOM-map-oriented machine-a partly custom-designed architecture compared to standard hardware; CompEuro'89.,'VLSI and Computer Peripherals. VLSI and Microelectronics, 1989   -  cited by 30  

R Hartenstein, M Herz, T Hoffmann, U Nageldinger: On reconfgurable co-processing units; Parallel and Distributed Processing, 1998, 67-72   -  cited by 28  

J Becker, R Hartenstein, M Herz, U Nageldinger: A novel sequencer hardware for application specific computing; Proc. ASAP`97, Zurich, Switzerland, July 14-16, 1997,   -  cited by 28  

A Ast, J Becker, R Hartenstein, R Kress, H Reinig, K Schmidt: Data-procedural Languages for FPL-based Machines; Field-Programmable Logic Architectures, Synthesis and Applications, 183-191, 4th Int. Workshop On Field Programmable Logic And Applications, FPL'94, Prague, September 7-10, 1994, Lecture Notes in Computer Science, Springer, 1994            -  cited by 27  

R Hartenstein: Hardware description languages; Elsevier Science Inc., 1987   -  cited by 27  

J Becker, R Hartenstein, R Kress, H Reinig: High-performance computing using a reconfigurable accelerator; Concurrency: Practice and Experience 8 (6), 1996, 429-443   -  cited by 24  

R Hartenstein, AG Hirschbiel, M Weber: MoM-Map Oriented Machine; E. Chiricozzi, A. D'Amico: Parallel Processing and Applications, North-Holland Pulishing Co. 1988   -  cited by 24  

R Hartenstein, M Herz, M Miranda, E Brockmeyer, F Catthoor: Memory addressing organization for stream-based reconfigurable computing; 9th IEEE International Conference on Electronics, Circuits and Systems - ICECS 2002, September 15-18, 2002, Dubrovnik, Croatia   -  cited by 23  

R Hartenstein, J Becker, R Kress, H Reinig: A novel machine paradigm to accelerate scientific computing; COMPUTER SCIENCE AND INFORMATICS 25, 1995, 2-16   -  cited by 23  

R Hartenstein, R Kress, H Reinig: A reconfigurable data-driven ALU for Xputers; FPGAs for Custom Computing Machines, 1994. Proceedings. IEEE Workshop on FPGAs for Custom Computing Machines, FCCM'94, Napa, CA., April 1994 - cited by 23  

R Hartenstein, AG Hirschbiel, M Weber: XPUTERS: An Open Family of Non-von Neumann Architectures; ARCS, 1990, 45-58   -  cited by 23  

R Hartenstein: The digital divide of computing; Proceedings of the 1st conference on Computing Frontiers, 2004, 357-362   -  cited by 22  

R Hartenstein, M Herz, T Hoffmann, U Nageldinger: Mapping applications onto reconfigurable KressArrays; Field Programmable Logic and Applications, 1999, 385-390   -  cited by 20  

R Hartenstein, R Kress, H Reinig: A dynamically reconfigurable wavefront array architecture for evaluation of expressions; Proc. Int'l. Conference on Application-Specific Array Processors, ASAP'94, San Francisco, 1994   -  cited by 19  

J. Becker, R. Hartenstein: Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators; 5th Int'l. Workshop on Hardware/Software Co-Design CODES/CASHE'97, Braunschweig, Germany, March 24-26,1997   -  cited by 18  

C Morra, J Becker, M Ayala-Rincon, R Hartenstein: FELIX: using rewriting-logic for generating functionally equivalent implementations; International Conference on Field Programmable Logic and Applications, 2005. ...   -  cited by 18  

M Ayala-Rincón, RB Nogueira, CH Llanos, RP Jacobi, R Hartenstein: Modeling a reconfigurable system for computing the FFT in place via rewriting-logic; Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th ...   -  cited by 18  

R Hartenstein, M Herz, T Hoffmann, U Nageldinger: Generation of design suggestions for coarse-grain reconfigurable architectures; Field-Programmable Logic and Applications 2000: The Roadmap to Reconfigurable ...   -  cited by 18  

J Becker, R Hartenstein: Performance analysis in CoDe-X partitioning for structural programmable accelerators; Proceedings of the 5th International Workshop on Hardware/Software Co-Design 1997   -  cited by 18  

R Hartenstein, R Kress, U Nageldinger: An operating system for custom computing machines based on the Xputer paradigm; Field-Programmable Logic and Applications, 1997, 304-313   -  cited by 18  

R Hartenstein: Basics of reconfigurable computing; Designing Embedded Processors, 2007, 451-501    -  cited by 17  

R Hartenstein, TH Hoffmann, U Nageldinger: Design-space exploration of low power coarse grained reconfigurable datapath array architectures; Integrated Circuit Design, 2000, 118-128   -  cited by 16  

M Ayala-Rincón, CH Llanos, RP Jacobi, R Hartenstein: Prototyping time-and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic; ACM Transactions on Design Automation of Electronic Systems (TODAES) 11, 2006 (2 ...   -  cited by 15  

H Grünbacher, R Hartenstein: Field-programmable Gate Arrays: Architecture and Tools for Rapid Prototyping: Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31-September 2, 1992: Selected Papers; Springer-Verlag      -  cited by 15  

R Hartenstein, AG Hirschbiel, M Weber: The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration; ICPP (1), 1990, 609-610   -  cited by 15  

A Ast, R Hartenstein, H Reinig, K Schmidt, M Weber: A General Purpose Xputer Architecture derived from DSP and Image Processing; VLSI Design Methodologies for Digital Signal Processing Architectures 1994, 365-394   -  cited by 14  

R Hartenstein, AG Hirschbiel, M Weber: Mapping systolic arrays onto the map-oriented machine (MoM); Proc. 3rd Int’l Conf. on Systolic Arrays, 1989, Kilarney, Ireland   -  cited by 14  

M Ayala-Rincón, RP Jacobi, LGA Carvalho, CH Llanos, R Hartenstein: Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic; Proceedings of the 17th symposium on Integrated circuits and system design ...2004   -  cited by 13  

R Hartenstein: Data-stream-based computing: Models and architectural resources; INFORMACIJE MIDEM-LJUBLJANA-. 33 (4), 2003, 228-235   -  cited by 13  

J Becker, R Hartenstein, M Herz, U Nageldinger: An embedded accelerator for real world computing; VLSI: Integrated Systems on Silicon, 1997, 215-226   -  cited by 13  

J Becker, R Hartenstein, M Herz, R Kress, U Nageldinger: A Parallelizing Programming Environment for Embedded Xputer-based Accelerators; High Performance Computing Symposium ‘96, Ottawa, Canada 1996   -  cited by 13 *  

J Becker, R Hartenstein, R Kress, H Reinig: High-performance computing using a reconfigurable accelerator; Proc. of Workshop on High Performance Computing, 1995, Montreal, Canada   -  cited by 13  

M Ayala-Rincón, RM Neto, RP Jacobi, CH Llanos, R Hartenstein: Applying ELAN strategies in simulating processors over simple architectures; Electronic Notes in Theoretical Computer Science 70 (6), 2002, 84-99   -  cited by 11  

H. Gruenbacher, R. Hartenstein: Field-Programmable Logic and Applications. The Roadmap to Reconfigurable Computing: 10th International Conference, FPL 2000 Villach, Austria, August 27-30, 2000 Proceedings; Springer      -  cited by 11  

F Gilbert, R Hartenstein, M Herz: Designing for xilinx xc6200 fpgas; Field-Programmable Logic and Applications From FPGAs to Computing Paradigm, 1998   -  cited by 11  

R Hartenstein, J Becker, R Kress: Two-level partitioning of image processing algorithms for the parallel map-oriented machine; Proc. 4th ACM/IEEE International Workshop on Hardware/ Software Co-Design Codes/CASHE/CODES'96, Pittsburgh, PA, USA, March 18 - 20, 1996   -  cited by 11  

G Alfs, R Hartenstein, A Wodtko: The KARL/KARATE system-automatic test pattern generation based on RT level descriptions; Test Conference, 1988. Proceedings. New Frontiers in Testing, International ... 1988   -  cited by 11  

G Girardi, R Hartenstein, U Welters: ABLED: A RT Level Schematics Editor and Simulator Interface; CVT report; Turino / Kaiserslautern 1985   -  cited by 11 1985  

R Hartenstein: Increasing hardware complexity—a challenge to computer architecture education; ACM SIGARCH Computer Architecture News 2 (4), 1973, 201-206   -  cited by 11  

R Hartenstein: The von Neumann Syndrome; Stamatis Vassiliadis Memorial Symposium, 2007   -  cited by 10  

R Hartenstein: Configware/Software Co-design: Be prepared for the next revolution; Proc. of the 5th IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS'02), Brno, Czechia, April 17 - 19, 2002   -  cited by 10  

R Hartenstein, R Kress, H Reinig: A Scalable, Parallel, and Reconfigurable Datapath Architecture; Sixth International Symposium on IC Technology, Systems & Applications, 1995.   -  cited by 10  

R Hartenstein, A Hirschbiel, M Weber: A flexible Architecture for Image Processing; Microprocessing and Microprogramming 21 (1), 1987, 65-71   -  cited by 10  

R Hartenstein, R. Zaks: Workshop on the Microarchitecture of Computer Systems, June 23-25, 1975, Nice, France, 1975; North-Holland Pub. Co.           dia show       -  cited by 10  

R Hartenstein: Microprogramming concepts-a step towards structured hardware design; Proc. 7th annual workshop on Microprogramming, Palo Alto, Cal., Sept. 1974, 59-65   -  cited by 10  


Christope Bobda: Introduction to Reconfigurable Computing: Architectures, algorithms and applications; Springer Verlag, 2007 -- reprinted 2009 and 2010             


*)  citation in: Damian Miller (mirror) ; Reconfigurable Systems: A Potential Solution to the von Neumann Bottleneck; Acceptance of Senior Honors Thesis, Liberty University. -  also referencing:
[7] R. Hartenstein. (2001, June). What is Morphware?. Available: http://morphware.de/
[8] R. Hartenstein. (2001, June). Data-stream-based Computing. Av.:  http://data-streams.org/#data
[9] R. Hartenstein. (2001, June). What is Flowware?  Available: http://flowware.net/
[10] R. Hartenstein. (2005, June). What is Configware?  Available: http://configware.org/

[12] R. Hartenstein, “Morphware and configware,” in Handbook of Nature-Inspired  and Innovative Computing: Integrating Classical Models with Emerging RECONFIGURABLE SYSTEMS Technologies, A. Y. Zomaya, Ed. New York: Springer Science + Business Media, Inc., 2006, pp. 343-386, doi:10.1007/0-387-27705-6_11

[17] R. Hartenstein, “Trends in reconfigurable logic and reconfigurable computing,” Proc. 9th International Conference on Electronics, Circuits, and Systems, vol. 2, pp. 801-808, December 2002, doi:10.1109/ICECS.2002.1046294