Search Criteria: Projects       Keyword: PATMOS

 

Power and Timing Modelling for Optimisation and Specification  (PATMOS)

Date of begin:1990-01-01           Date of completions:1992-06-30

Project acronym: PATMOS            Project status: Completed

The PATMOS conference series  [x], the oldest annual conference series on low power design,  is a spin-off of this PATMOS project

Coordinator:

Name of the Organisation: TECHNISCHE UNIVERSITAET KAISERSLAUTERN
administrative contact partner Address
Name: Reiner HARTENSTEIN  Postfach 3049
Erwin Schroedinger Strasse 46
67663  KAISERSLAUTERN
DEUTSCHLAND

Tel:+49-631-2052606

Fax:+49-631-2052640

Goals: This Action aims to develop a method of modelling, optimising and specifying the power and timing of very high-speed integrated circuits (VHSICs) using technologies such as GaAs, CMOS, BiCMOS, SOS, SOI and ECL. An experimental implementation will apply methods of performance and power modelling for VHSICs to optimising complex digital system designs. The new approach should work for conservative technologies as well.

Results: A new method to cope with the design of very complex and high speed circuits and systems is being developed. This method will enable system designers who are not specialists at near-silicon levels to implement high-performance circuits. The method will be implemented in an experimental system and applied to selected circuit design examples. The action has concentrated on the following aspects:

power estimation of regular structures;
statistical power estimation (synchronised event power model);
timing modelling by abstraction;
characterization of interconnect;
characterization of cells;
circuit extraction of parameters in multiconductor transmission lines.

General Informationen: APPROACH AND METHODS
The first tasks are to define:
-methods for modelling interconnects and devices in the power and timing domain
-a notation for the adaptation of the methods adopted to different technologies
-a method to extract all data needed from the layout.
Methods will then be developed for implementation in an experimental system that will be validated and evaluated with respect to selected GaAs and CMOS circuit design examples.
PROGRESS AND RESULTS
The action has concentrated on the following aspects:
-power estimation of regular structures
-statistical power estimation (synchronised event power model)
-timing modelling by abstraction
-characterisation of interconnect
-characterisation of cells
-circuit extraction supporting interconnect modelling
-accurate extraction of parameters in multiconductor transmission lines
POTENTIAL
The results of the Action will form the basis of a design for performance methods for complex VHSICs adaptable to a wide variety of technologies. The effect of the method being developed will be a substantial reduction in the frequency of reimplementationof an important class of CAE tools.

Project reference: 3237      Programm-acronym: ESPRIT 2

Program type: Second Framework Programme

Theme index code: Electronics, Microelectronics, Information Processing, Information Systems

Other Partners:

Name of the Organisation:  TELECOM PARIS  University
administrative cooperation partner Address

Name: Michel DANA 

46 RUE BARRAULT
75634    PARIS,  FRANCE

Region: ÎLE DE FRANCE Ile de France Paris

Prof. Dr. Elmar Melcher, at that time a Ph. D. student, has been a member of the PATMOS team.

Tel:+33-1-45817597

Fax:+33-1-45807247

Email:Contact

 
Name of the Organisation: UNIVERSIDAD POLITECNICA DE CANARIAS
administrative cooperation partner  Address

Name: Antonio NUNEZ 

Dept. de Electronica y Telecommunicacion
CAMPUS UNIVERSITARIO DE TAFIRA
35017  LAS PALMAS DE GRAN CANARIA,  ESPAÑA

Region: CANARIAS Canarias Las Palmas
Prof. Francis Jutand, at that time with the Telecom Paris University, has also been a PATMOS partner leader.

Tel:+34-28-451250

Fax:+34-28-451243

Email:Contact