Stoffsammlung
last update: January 2019
-- meine diversen Publikationslisten durchsehen !!!!!
untersuche FPGAs for Software Programmers (FSP) !!!!!! Siehe Workshop WM1 FPGAs for Software Programmers (FSP) !!!!!!

Nachiket Kapre: Survey of DomainSpecific Languages for FPGA Computing (FPL'16)

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Reconfigurable Computing - From Embedded Systems to Reconfigurable Hyperscale Servers Organizers: Mario Porrmann (Bielefeld University, DE), Zain Ul-Abdin (Halmstad University, SE), and Madhura Purnaprajna (Amrita University, IN)

FPGAs for Software Programmers (FSP 2016) Organizers: Andreas Koch (Technische Universität Darmstadt, DE) and Markus Weinhardt

Tutorial TF3 Accelerating Big Data Processing with Hadoop, Spark, and Memcached on Datacenters on Modern Clusters Organizers: DK Panda and Xioyi Lu (The Ohio State University, US)

Tutorial TM3 Energy-efficient Acceleration for Neuro-inspired Computing On-a-Chip Organizers: Yu Cao, Jae-sun Seo, and Yu Wang (Arizona State University, US)

A Software Developer's Journey into a Deeply Heterogeneous World (slides) Tomas Evensen Xilinx, US

Accelerating Datacenter Workloads (slides) P. K. Gupta Intel, US

Heterogeneous Computing Systems in Cloud Datacenters (slides) Christoph Hagleitner IBM, CH

A Survey on Reconfigurable Accelerators for Cloud Computing Christoforos Kachris, Dimitrios Soudris FPL'17

Keynote K5: A Software Developer's Journey into a Deeply Heterogeneous World Tomas Evensen (Xilinx, US) Chair: Jason Anderson FPL'17

Efficient and Reliable High-Level Synthesis Design Space Explorer for FPGAs Dong Liu, Benjamin Carrion Schafer Hong Kong Polytechnic University FPL'16

Keynote K4: Accelerating Datacenter Workloads P. K. Gupta (Intel, US) FPL'16

Designing a Virtual Runtime for FPGA Accelerators in the Cloud? Mikhail Asiatici1, Nithin George1, Kizheppatt Vipin2, Suhaib A. Fahmy3, Paolo Ienne1 1EPFL FPL'16

FPGA-based Accelerator Design from a Domain-Specific LanguageOliver Reiche, Frank Hannig, Akif Oezkan, Jürgen Teich, Erlangen FPL'16

LYNX: CAD for FPGA-Based Networks-on-Chip Mohamed Abdelfattah, Vaughn Betz University of Toronto, CA FPL'16

Accelerating Recurrent Neural Networks in Analytics Servers: Comparison of FPGA, CPU, GPU, and ASIC, Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit Mishra, Srivatsan Krishnan, Debbie Marr, Intel, US. FPL'16

SLIDES LINK -- Search-Based Synthesis of Approximate Circuits Implemented into FPGAs, Zdenek Vasicek, Lukas Sekanina, Brno University of Technology, CZ, FPL'16

SLIDES --- Keynote K1: Configurable Clouds; Doug Burger (Microsoft, US), FPL'16 ⯇ ⯇ ⯇ ⯇ ⯇

CREC: A Novel Reconfigurable Computing Design Methodology - RAW'03 - ppt

Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability." - RAW'03 - ppt

Performance and Overhead in a Hybrid Reconfigurable Computer."" - RAW'03 - ppt

Remote and Partial Reconfiguration of FPGAs: tools and trends. - RAW'03 - ppt

Effective Utilization and Reconfiguration of Distributed Hardware Resources Using Job Management Systems. - RAW'18 - ppt

Redundant Binary to Two's Complement Converter on FPGAs through Fabric Aware Scan Based Encoding Approach for Fault Localization Support" - RAW'03 -

Keynote 1: Heterogeneous Technology Configurable Fabrics: Leveraging Reconfiguration as a Pathway Towards Emerging Devices" - RAW'17

On How to Improve FPGA-Based Systems Design Productivity via SDAccel" - RAW'16 - ppt

A rapid prototyping method to reduce the design time in commercial high-level synthesis tools" - RAW'16 - ppt

A fully parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications" - RAW'16 - ppt

Clustering and Mapping Algorithm for Application Distribution on a Scalable FPGA Cluster - RAW'16 - ppt

A Fast and Accurate Cost Model for FPGA Design Space Exploration in HPC Applications - RAW'16 - ppt

High Throughput Large Scale Sorting on a CPU-FPGA Heterogeneous Platform - RAW'16 - ppt

Resource-Efficient Scheduling for Partially-Reconfigurable FPGA-based Systems - RAW'16 - ppt

Unleashing so,ware developers - RAW'13 - pdf

The All Programmable SOC FPGA at the Heart of Embedded Systems - RAW'13 - ppt

"A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture", Michael Hübner - RAW'11 -

RAW Keynote 2 - Tarek El-Ghazawi, George Washington University, "The Challenges of Computing with FPGAs" (Session Chair: Viktor Prasanna) - RAW'11 -

Programming Customized Parallel architectures in FPGA - RAW'10 - pdf

Advancing NASA's On-Board Processing Capabilities with Reconfigurable FPGA Technologies: Opportunities & Implications - RAW'10 - pdf

Fast dynamic and partial reconfiguration Data Path with low Hardware overhead on Xilinx FPGAs Michael Hübner, Diana Göhringer, Juanjo Noguera and Juergen Becker - RAW'10 -

CAP-OS: Operating System for Runtime Scheduling, Task Mapping and Resource Management on Reconfigurable Multiprocessor Architectures Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo and Jürgen Becker - RAW'10 - ppt

An Architectural Space Exploration Tool for Domain Specific Reconfigurable Computing Gayatri Mehta and Alex K. Jones " - RAW'10 -

keynote Reiner Hartenstein - RAW'10 - ppt

A Novel Hardwired NOC Framework with Unified Configuration and Functional Architectures Muhammad Aqeel Wahlah and Kees Goossens- RAW'10 -

A Low Cost and Adaptable Routing Network for Reconfigurable Systems Ricardo Ferreira, Marcone Laure, Thiago Lo, Antonio Carlos Beck and Luigi Carro- RAW'10 -

RDMS: A Hardware Task Scheduling Algorithm for Reconfigurable Computing Miaoqing Huang, Harald Simmler, Serres Olivier and Tarek El-Ghazawi - RAW'10 -

RAW Keynote - Rainer Hartenstein RAW'09 - ppt

Runtime Decision of Hardware or Software Execution On A Heterogeneous Reconfigurable Platform Vlad Sima and Koen Bertels- RAW'09 -

(Re-)Configurable Solutions for the high-volume ASSP Market- RAW'08 - ppt

Automatic Topology Optimization for FPGA Interconnect Synthesis - FPL'18 - pdf

Customizing Low-Precision Deep Neural Networks For FPGAs" - FPL'18 - pdf

Accelerating database systems using FPGAs: A survey - FPL18 - pdf

A Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA - FPL'18 - pdf

f-CNNx: A Toolflow for Mapping Multiple Convolutional Neural Networks on FPGAs - FPL'18 - pdf

An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug - FPL'18 - pdf

Facilitating Easier Access to FPGAs in the Heterogeneous Cloud Ecosystems - FPL'18 - pdf

"All Programmable FPGA, providing hardware efficiency to software programmers", Ivo Bolsens, Xilinx - FPL'17 - pdf

"The Era of Accelerators", Viktor K. Prasanna, University of Southern California - FPL'17 - pdf

"FPGAs in space: current experiences, future challenges and opportunities", David Merodio Codinachs, ESA - FPL'17 - pdf

FPGA design and prototyping @ Refter - FPL'17 - pdf

Accelerating Recurrent Neural Networks in Analytics Servers: Comparison of FPGA, CPU, GPU, and ASIC" >Accelerating Recurrent Neural Networks in Analytics Servers: Comparison of FPGA, CPU, GPU, and ASIC - FPL'16 - pdf

Optimizing Interconnection Complexity for Realizing Fixed Permutation in Data and Signal Processing Algorithms Ren Chen, Viktor Prasanna- FPL'16 - pdf

FMER: A Hybrid Configuration Memory Error Recovery Scheme for Highly Reliable FPGA SoCs - FPL'16 - pdf

Accelerating Particle Identification for High-speed Data-filtering Using OpenCL on FPGAs and Other Architectures - FPL'16 - pdf

Efficient and Reliable High-Level Synthesis Design Space Explorer for FPGAs - FPL'16 - pdf

Configurable Clouds - FPL'16 - ppt

Data Processing on the Fast Lane FPL'16 - ppt

Heterogeneous Computing Systems in Cloud Datacenters - FPL'16 - ppt

A Software Developer's Journey into a Deeply Heterogeneous World - FPL'16 - ppt

Tutorial TM1 Embedded Design Using LabVIEW Real-Time and FPGA Organizers: Jose Albuquerque Silva, Maha Moatemri, and Joseph Tagg (National Instruments, US)- FPL'16 -

Tutorial TM2 Hyperscale FPGA Research on Catapult Organizers: Andrew Putnam (Microsoft, US) and Derek Chiou (Microsoft and University of Texas Austin, US)- FPL'16

Tutorial TF3 Accelerating Big Data Processing with Hadoop, Spark, and Memcached on Datacenters on Modern Clusters Organizers: DK Panda and Xioyi Lu (The Ohio State University, US) - FPL'16 html

Automated Synthesis of FPGA-Based Heterogeneous Interconnect Topologies - FPL'13 -

Rapid FPGA Design Prototyping Through Preservation of System Logic: A Case Study - FPL'13 -

A Platform-Independent Runtime Methodology for Mapping Multiple Applications onto FPGAs Through Resource Virtualization - FPL'13 -

High-level linear projection circuit design optimization framework for FPGAs under over-clocking - FPL'12 - pdf

EmPower: FPGA based Rapid prototyping of dynamic power management algorithms for multi-processor systems on chip - FPL'12 - pdf

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