Workshop on
Reconfigurable
Systems for HPC (RHPC)
to be held in conjunction with
HPC Asia 2004
Date : July 21, 2004 (half day)
Place : Omiya Sonic City, Tokyo Area, Japan
Workshop organizer: Kazuaki Murakami, Kyushu Univ.
(murakami@i.kyushu-u.ac.jp)
Workshop Overview :
Today, in addition to conventional FPGA, some commercially available
(dynamically
or statically) reconfigurable@hardware/logic/processor/systems are
emerging.
These systems seem toward computation-intensive integer applications,
but
they intrinsically have potentials to be applied to floating-point
computations.
This workshop will discuss a broad view of the relationship between
reconfigurable
architectures and their applications to (integer and floating-point)
high-performance
computing.
Program:
Workshop on Reconfigurable Systems for HPC (RHPC)
14:00-17:35 Wednesday, July 21, 2004
*14:00-15:30 Session 1
14:00-14:05 Opening Remarks
14:05-14:50 Invited Talk: Reconfigurable HPC: Torpedoed by Deficits in
Education ?
Dr.-Ing. Reiner Hartenstein (TU Kaiserslautern)
14:50-15:10 Design Considerations of a Meta-Level Optimizing Computer
System (Short)
Fumihito Furukawa, Moriyuki Saito, Gaku Ishihara, Kanemitsu Ootsu,
Takashi Yokota, Takanobu Baba (Utsunomiya Univ.)
15:10-15:30 Reconfigurable Neural Network Using DAP/DNA (Short)
Yunqing Yu, Kazuaki Murakami (Kyushu Univ.)
*16:00-17:30 Session 2
16:00-16:30 Outline of the Ultra Fine Grained Parallel Processing by FPGA
(Regular)
Y. Inoguchi (JAIST)
16:30-17:00 SysteMoprh: Dynamic/Online/Adaptive System-Level Optimization
for SoC (Regular)
Norifumi Yoshimatsu, Takeshi Soga, Makoto Yoshida (FLEETS), Makoto Shuto
(ISIT), Yasuyuki Tanoue, Yosuke Fujii, Kazuhito Eshima, Takanori Hayashida,
Kazuaki Murakami (Kyushu Univ.)
17:00-17:30 Invited Talk: A Coarse-Grained Reconfigurable Architecture
Supporting Flexible Execution
Tetsuo Hironaka, Takeshi Fukuda, Yoshito Goto, Kazuya Tanigawa, Takashi
Kawasaki, Akira Kojima (Hiroshima City Univ.)
17:30-17:35 Closing Remarks
Topics of
Interest:
The topics of interests within the domain of reconfigurable systems for
high performance computing will include but are not limited to:
- Reconfigurable architectures/microarchitectures and systems
- Dynamically reconfigurable architectures
- Low power reconfigurable circuits and systems
- Customizable computing engines
- Embedded reconfigurable systems
- Reconfigurable-aware compilers and operating systems
- Integrated software/hardware solutions
- Applications of reconfigurable systems
- Algorithms implemented on reconfigurable logic
- Design flow, Platform-based design
- Optimization, technology mapping, system-level partitioning
- Testing, verification and benchmarking of reconfigurable
circuits and systems
- Roadmaps in technology, applications and design
- Surveys and architecture classification
Paper
Submission Guidelines:
The workshop organizers solicit submissions describing novel research and
development as well as applications of reconfigurable logic for HPC. The
authors are invited to submit a proposal in either of the following ways:
| (a) |
Submit a full paper in PDF format (max. 8 pages) which will appear on proceedings
of the workshop.
|
| (b) |
Submit an extended abstract in PDF format (max. 2 pages), which will appear
on proceedings of the workshop, and the corresponding presentation slides
in Microsoft Powerpoint or PDF format (max. 30 slides). |
The submissions page is now open. (If you
want to submit a file whose size is larger than 5MB, please send mail
to baba@c.csce.kyushu-u.ac.jp.).
Organizer:
Kazuaki Murakami (System LSI Research Center, Kyushu Univeristy)
Important Dates:
Paper submission deadline
|
March 15, 2004
|
Acceptance notification
|
April 5, 2004
|
Camera-ready deadline
|
May 7, 2004
|
Contact : rhpc-info@slrc.kyushu-u.ac.jp