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The PISA Page

- Prof. Dr.-Ing. Reiner Hartenstein

  

  

TU Kaiserslautern

last update in 2012 of very old stuff  -  but the trailblazing achievements reported here have still an impact  --  citations

The PISA project and the DPLA

The PISA project in the 80ies at Kaiserslautern Xputer Lab implemented an ultra-fast integrated circuit Design Rule Check (DRC) based on Reconfigurable Computing (RC)  [1 - 7] and the (non-von-Neumann) anti machine paradigm [8 - 12]. Compared to state-of-the-art DRC software speed-ups up to a factor of 15000 have been obtained. Also the complexity properties of the PISA solution are linear with the area size of the design, which is drastically better than with all other DRC implementations. Serving Lambda-grid-based design rules à la Lynn Conway, PISA used image processing methods representing the design rule violations as a collection of 4-by-4-pixel patterns. To avoid needing 256 FPGAs of state of the art at that time a single PLA-based chip called DPLA (Dynamically Programmable Logic Array [8]) did the job, which has been designed and fabricated via the MPC infrastructure of the multi-university E.I.S. project. Because no routing was needed as known from FPGAs, the DPLAs massively higher transistor density can be utilized, since all design rule violation patterns are represented by a set of canonical Boolean expressions. The PISA systrem was running on the Xputer Lab's MoM anti machine architecture [1 - 8].


A Novel ASIC Design Approach  [1]   R. W. Hartenstein, M. Riedmuller, K. Schmitt, M. Weber: A Novel Asic Design Approach Based on a New Machine Paradigm; Special Issue of IEEE Journal of Solid State Circuits, July 1991  -  http://www.fpl.uni-kl.de/xputer-pages/Xputer-paper-040.pdf
 
A Novel Compilation Technique for HPRC   [2]   R. W. Hartenstein, K. Schmidt, H. Reinig, M. Weber: A Novel Compilation Technique for a Machine Paradigm Based on Field-Programmable Logic; Proc. FPL 1991, Oxford, UK - http://www.fpl.uni-kl.de/xputer-pages/Xputer-paper-039.pdf
 
Simple High Performance Hardware   [3]   R.W. Hartenstein, A.G. Hirschbiel, M.Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware; InfoJapan'90- International Conference memorating the 30th Anniversary of the Computer Society of Japan, Tokyo, Japan, 1990 - http://www.fpl.uni-kl.de/xputer-pages/Xputer-paper-031.ps  http://www.fpl.uni-kl.de/xputer-pages/InfoJapan-paper-031.pdf
 
The Novel Parallel Computation Paradigm   [4]   R. Hartenstein, A. Hirschbiel, K. Schmidt, M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW; Future Generation Computer Systems 7 91/92, p. 181-198, North Holland (nvited reprint of Paper 31) - http://www.fpl.uni-kl.de/xputer-pages/Xputer-paper-042.pdf  citations
 
A disruptive Machine Paradigm   [5]   R.W. Hartenstein, A.G. Hirschbiel, M. Riedmueller, K. Schmidt, M.Weber: A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS-24, Hawaii Int. Conference on System Sciences, Koloa Hawaii, 1991 - Second Best Paper Award (Honorable Mention)  - http://www.fpl.uni-kl.de/xputer-pages/Xputer-paper-036.pdf
 
Best Paper and Best Presentation Award   [6]   R.W. Hartenstein, A.G. Hirschbiel, M. Riedmuller, K. Schmidt, M.Weber: Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Preprocessing; 12. DAGM-Symposium Mustererkennung, Oberkochen-Aalen, 1990  Best Paper and Best Presentation Award (DM 1000.--) - Speaker: Michael Weber  - http://www.fpl.uni-kl.de/xputer-pages/Xputer-paper-029.pdf

 
St. Charles, Illinois   [7]   R.W. Hartenstein, A.G. Hirschbiel, M.Weber: The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration; 1990 Int. Conference on Parallel Processing, St. Charles, Illinois , 1990 - http://www.fpl.uni-kl.de/xputer-pages/Xputer-paper-027.pdf --  read the conference book

 

    [8]   Dale Meinks, Andreas Pietsch: Xputer; (in German), 2005, Weblearn Archive, EECS dept., Bremen Univ. of Applied Sciences, http://www.weblearn.hs-bremen.de/risse/RST/ws99/Xputers/xputer.htm    http://www.weblearn.hs-bremen.de/risse/RST/ws99/Xputers/xputer.pdf     mirror

 

    [9]   R. Hartenstein, R. Hauck, A. Hirschbiel, W. Nebel, M. Weber: PISA, a CAD package and special hardware for pixel-oriented layout analysis; Report, Univ. Kaiserslautern, 1984
 
 
  [10]   (R. Hartenstein,  R.Hauck, A.Hirschbiel, W.Nebel, M.Weber) PISA - A CAD package and special hardware for pixel-oriented layout analysis, ICCAD, Santa Clara, 1984, IEEE, New York 1984
 
    [11]   R. Hartenstein: VLSI-System-Entwurf; Kursunterlagen für die CCG (Carl-Cranz-Ges., c/o DLR Oberpfaffenhofen), 5-tägiger Kurs in Oberpfaffenhofen (Bayern) 1984 -
 
    [12]   (R. Hartenstein,  J. Bloedel, R.Hauck, M. Ryba, H.Salzmann, M.Weber) PISA user manual; report, Kaiserslautern 1985


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