Power and Timing Modelling for Optimisation and Specification

Start date:1990-01-01                   End date:1992-06-30

Project Acronym:PATMOS       Project status:Completed

Coordinator

Organization name:TECHNISCHE UNIVERSITAET KAISERSLAUTERN
Administrative contact Address
Name:Reiner HARTENSTEIN  P.F. 3049
Erwin Schroedinger Strasse 46,  67663    KAISERSLAUTERN    DEUTSCHLAND

Region:RHEINLAND-PFALZ RHEINHESSEN-PFALZ Kaiserslautern, Kreisfreie Stadt
Tel:+49-631-2052606
Fax:+49-631-2052640
E-mail: Contact
URL: Organization Type:  Education

Description
Objective: This Action aims to develop a method of modelling, optimising and specifying the power and timing of very high-speed integrated circuits (VHSICs) using technologies such as GaAs, CMOS, BiCMOS, SOS, SOI and ECL. An experimental implementation will apply methods of performance and power modelling for VHSICs to optimising complex digital system designs. The new approach should work for conservative technologies as well.
Achievements: A new method to cope with the design of very complex and high speed circuits and systems is being developed. This method will enable system designers who are not specialists at near-silicon levels to implement high-performance circuits. The method will be implemented in an experimental system and applied to selected circuit design examples. The action has concentrated on the following aspects:

  power estimation of regular structures;
statistical power estimation (synchronised event power model);
timing modelling by abstraction;
characterization of interconnect;
characterization of cells;
circuit extraction of parameters in multiconductor transmission lines.

General information: APPROACH AND METHODS
The first tasks are to define:
-methods for modelling interconnects and devices in the power and timing domain
-a notation for the adaptation of the methods adopted to different technologies
-a method to extract all data needed from the layout.
Methods will then be developed for implementation in an experimental system that will be validated and evaluated with respect to selected GaAs and CMOS circuit design examples.
PROGRESS AND RESULTS
The action has concentrated on the following aspects:

  -power estimation of regular structures
-statistical power estimation (synchronised event power model)
-timing modelling by abstraction
-characterisation of interconnect
-characterisation of cells
-circuit extraction supporting interconnect modelling
-accurate extraction of parameters in multiconductor transmission lines

POTENTIAL
The results of the Action will form the basis of a design for performance methods for complex VHSICs adaptable to a wide variety of technologies. The effect of the method being developed will be a substantial reduction in the frequency of reimplementationof an important class of CAE tools.

Project Details
Start date:1990-01-01
End date:1992-06-30
Duration:
Project Reference:3237
Project cost:
Project Funding:
Programme Acronym: ESPRIT 2
Programme type:Second Framework Programme
Subprogramme Area:
Contract type:No contract type
URL:
Subject index:Electronics, Microelectronics, Information Processing, Information Systems

Other participants:

Organization name:TELECOM PARIS
Administrative contact Address
Name:Michel DANA  46 RUE BARRAULT,  75634 PARIS,  FRANCE

Region:ÎLE DE FRANCE Ile de France Paris
Tel:+33-1-45817597
Fax:+33-1-45807247
E-mail: Contact
URL: Organization Type:
 
Organization name:UNIVERSITAT POLITECNICA DE CANARIAS
Administrative contact Address
Name:Antonio NUNEZ  Dept. de Electronica y Telecommunicacion
CAMPUS UNIVERSITARIO DE TAFIRA
35017  LAS PALMAS DE GRAN CANARIA,  ESPAÑA

Region:CANARIAS Canarias Las Palmas
Tel:+34-28-451250
Fax:+34-28-451243
E-mail: Contact
URL: Organization Type:
 

Record control number:8208

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