DPLA: much more efficient than FPGAs

Reiner Hartenstein, TU Kaiserslautern, November 2015

The Reconfigurable Computing Paradox (RC Paradox): much more area-inefficient than microprocessors, FPGAs are excellent accelerators. It’s because of the paradigm shift: away from von Neumann. For some special purpose applications much more area-efficient accelerators like PLAs can be used: but only for canonical Boolean expressions. To accelerate a Mead-&-Conway design rule check (PISA project) we would have needed 256 FPGAs under Moore’s law of the mid’ 80ies. For a PLA-based solution we needed only a single “DPLA” chip designed by us and manufactured by the MPC infrastructure of the E.I.S. project. We obtained a speed-up factor of 15.000 – 25 years earlier than comparable results from the FPGA speed-up culture. For details see references [11] - [42] in our WRCE-2006 paperAlso see slide no. 10 within the PATMOS 25th Anniversary Paper.

DPLA was implemented as a special kind of FPGA, also called FPCA.

This acronym stands for Field-Programmable Canonical Logic Array.